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CS5466 Low-cost Power/Energy IC with Pulse Output
Features
Single-chip Power Measurement Solution Energy Data Linearity:
0.1% of Reading, over 1000:1 Dynamic Range
Description
The CS5466 is a low-cost power meter solution incorporating dual delta-sigma () analog-to-digital converters (ADCs), an energy-to-frequency converter, and energy pulse outputs on a single chip. The CS5466 is designed to accurately measure and calculate energy for single phase, 2- or 3-wire power metering applications with minimal external components. The low-frequency pulse outputs, E1 and E2, provide pulses at a frequency which is proprtional to the active power and can be used to drive a stepper motor or a mechanical counter. Energy direction output, NEG, indicates when pulse outputs E1 and E2 represent negative active power. The high-frequency pulse output FOUT is designed to assist in system calibration. The CS5466 has configuration pins which allow for direct configuration of pulse output frequency, current channel input range, and high-pass filter enable option. The CS5466 also has a power-on reset function which holds the part in reset until the supply reaches an operable level. ORDERING INFORMATION
See page 16.
On-chip functions: Measures Power and Performs Energy-to-pulse Conversions Meets Accuracy Spec for IEC, ANSI, & JIS. High-pass Filter Option Four Input Ranges for Current Channel On-chip, 2.5 V Reference Pulse Outputs for Stepper Motor or Mechanical Counter On-chip Energy Direction Indicator Ground-referenced Input Signals with Single Supply High-frequency Output for Calibration On-chip, Power-on Reset (POR) Power Supply Configurations:
VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to 5 V
I
VA+
RESET
VD+
IIN+ IIN-
PGA
4th Order Modulator
Digital Filter
HPF
Option
FOUT Energy-toFrequency Conversion E1 E2 NEG
VREFIN
x1
HPF FREQ0 Config FREQ1 FREQ2 IGAIN0 IGAIN1 CPUCLK XOUT XIN
VIN+ VIN-
x10
2nd Order Modulator
Digital Filter
HPF
Option
VREFOUT
2.5V On-Chip Reference
Clock Generator
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
AUG `05 DS659F1
CS5466
TABLE OF CONTENTS
1. OVERVIEW ............................................................................................................................... 3 2. PIN DESCRIPTION ................................................................................................................... 4 3. CHARACTERISTICS & SPECIFICATIONS ............................................................................. 5 RECOMMENDED OPERATING CONDITIONS ....................................................................... 5 ANALOG CHARACTERISTICS ................................................................................................ 5 VOLTAGE REFERENCE ......................................................................................................... 6 DIGITAL CHARACTERISTICS ................................................................................................. 7 SWITCHING CHARACTERISTICS .......................................................................................... 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 9 4. THEORY OF OPERATION ..................................................................................................... 10 4.1 Digital Filters .................................................................................................................... 10 4.2 Active Power Computation ............................................................................................... 10 5. FUNCTIONAL DESCRIPTION ............................................................................................... 11 5.1 Analog Inputs ................................................................................................................... 11 5.1.1 Voltage Channel .................................................................................................. 11 5.1.2 Current Channel .................................................................................................. 11 5.2 High-pass Filter ................................................................................................................ 11 5.3 Energy Pulse Outputs ...................................................................................................... 11 5.3.1 Pulse Output Format. .......................................................................................... 11 5.3.2 Selecting Frequency of E1 and E2 ...................................................................... 11 5.3.3 Selecting Frequency of FOUT ............................................................................. 12 5.3.4 Absolute Max Frequency on E1 and E2 .............................................................. 12 5.3.5 E1 and E2 Frequency Calculation ....................................................................... 13 5.4 Energy Direction Indicator ............................................................................................... 13 5.5 Power-on Reset ............................................................................................................... 13 5.6 Oscillator Characteristics ................................................................................................. 13 5.7 Basic Application Circuit .................................................................................................. 14 6. PACKAGE DIMENSIONS ....................................................................................................... 15 7. REVISION HISTORY................................................................................................................ 16
LIST OF FIGURES
Figure 1. Timing Diagram for E1, E2 and FOUT (Not to Scale) ...................................................... 8 Figure 2. Data Flow ....................................................................................................................... 10 Figure 3. Oscillator Connection ..................................................................................................... 13 Figure 4. Typical Connection Diagram .......................................................................................... 14
LIST OF TABLES
Table 1. Current Channel PGA Setting ......................................................................................... 11 Table 2. Maximum Frequency for E1, E2, and FOUT ................................................................... 12 Table 3. Absolute Max Frequency on E1 and E2.......................................................................... 12
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1. OVERVIEW
The CS5466 is a CMOS monolithic power measurement device with an energy computation engine. The CS5466 combines a programmable gain amplifier, two ADCs, and energy-to-frequency conversion circuitry on a single chip. The CS5466 is designed for energy measurement applications and is optimized to interface to a shunt or current transformer for current measurement, and to a resistive divider or transformer for voltage measurement. The current channel has a programmable gain amplifier (PGA) which provides four full-scale input options. With a single +5 V supply on VA+/AGND, both of the CS5466's input channels accommodate common-mode plus signal levels between (AGND - 0.25 V) and VA+. The CS5466 has three pulse output pins: E1, E2, and FOUT. E1 and E2 can be used to directly drive a mechanical counter or stepper motor, or interface to a microcontroller. The FOUT pin conveys active (real) power at a pulse frequency many times higher than that of the E1 or E2 pulse frequency, allowing for high-speed calibration.
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2. PIN DESCRIPTION
XOUT CPUCLK VD+ DGND IGAIN0 NEG IGAIN1 HPF VIN+ VINVREFOUT VREFIN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 XIN FREQ0 E1 E2 FREQ1 RESET FOUT FREQ2 IIN+ IINVA+ AGND Crystal In Frequency Select 0 Energy Output 1 Energy Output 2 Frequency Select 1 Reset High-frequency Output Frequency Select 2 Differential Current Input Differential Current Input Positive Analog Supply Analog Ground
Crystal Out CPU Clock Output Positive Power Supply Digital Ground Gain Select 0 Negative Energy Indicator Gain Select 1 High-pass Filter Enable Differential Voltage Input Differential Voltage Input Voltage Reference Output Voltage Reference Input
Clock Generator Crystal Out Crystal In CPU Clock Output Control Pins Gain Select Frequency Select High Pass Filter Enable Reset Energy Pulse Outputs Energy Output High Freq Output Neg Energy Indicator Analog Inputs/Outputs Differential Voltage Inputs Voltage Reference Output Voltage Reference Input Differential Current Inputs Power Supply Connections Positive Digital Supply Digital Ground Analog Ground Positive Analog Supply 3 4
1, 24
XOUT, XIN - A single stage amplifier inside the chip is connected to these pins and can be used with a crystal to provide the system clock for the device. Alternatively, an external clock can be supplied to the XIN pin to provide the system clock for the device. CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.
2 5, 7 8 19 22, 21 18 6 9, 10 11 12 16, 15
IGAIN1, IGAIN0 - Used to select the current channel input gain range.
17, 20, 23 FREQ2,FREQ1,FREQ0 - Used to select max pulse output frequency for E1, E2, and FOUT.
HPF - High disables the HPF. Low activates HPF on Voltage channel. Connecting HPF pin to FOUT pin activates HPF on Current channel. RESET - Low activates Reset.
E1, E2 - Active low alternating pulses with an output frequency that is proportional to the active (real) power. FOUT - Outputs energy pulses at a frequency higher than E1 and E2 outputs. Used for calibration purposes. NEG - High indicates negative energy.
VIN+, VIN- - Differential analog input pins for voltage channel. VREFOUT - The on-chip voltage reference output pin. The voltage reference has a nominal magnitude of 2.5 V and is referenced to the AGND pin on the converter. VREFIN - Voltage input to this pin establishes the voltage reference for the on-chip modulators. IIN+, IIN- - Differential analog input pins for current channel.
VD+ - The positive digital supply. DGND - Digital Ground. AGND - Analog Ground. VA+ - The positive analog supply.
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3. CHARACTERISTICS & SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter Positive Digital Power Supply Positive Analog Power Supply Voltage Reference Specified Temperature Range Symbol VD+ VA+ VREFIN TA Min 3.135 4.75 -40 Typ 5.0 5.0 2.5 Max 5.25 5.25 +85 Unit V V V C
ANALOG CHARACTERISTICS
* * * Min / Max characteristics and specifications are guaranteed over all operating ponditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = 5 V 5% VD+ = 3.3 V 5% or 5 V 5%; AGND = DGND = 0 V. All voltages with respect to 0 V. MCLK = 4.096 MHz
*
Parameter Analog Inputs (Current Channel) Differential Input Range [(IIN+)-(IIN-)] (Gain = 10) (Gain = 50) (Gain = 100) (Gain = 150) (All Gain Ranges) (All Gain Ranges) [(VIN+)-(VIN-)]
Symbol IIN
Min 30 2
Typ 250 50 25 16.7 25 0.2 -
Max 250 -
Unit mV mV mV mV pF k mV pF M
Input Capacitance Effective Input Impedance Analog Inputs (Voltage Channel) Differential Input Range Input Capacitance Effective Input Impedance Accuracy (Energy Outputs) Active Energy Linearity (Note 1) Full-scale Error Offset Error
CinI ZinI VIN CinV ZinV
All Gain ranges Input Range 0.1% - 100% (Note 2) (Note 2)
-
-
0.1 4.0 0.06
-
% %FS %FS
Notes: 1. Applies when the HPF option is enabled
2. Applies before system calibration. Specified as a percentage of full scale (FS).
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ANALOG CHARACTERISTICS (Continued)
Parameter Power Supplies Power Supply Currents IA+ ID+ (VA+ = VD+ = 5 V) ID+ (VA+ = 5 V, VD+ = 3.3 V) (VA+ = VD+ = 5 V) (VA+ = 5 V, VD+ = 3.3 V) PSRR 45 56 1.3 2.9 1.7 21 11.6 55 75 25 mA mA mA mW mW dB dB Symbol Min Typ Max Unit
Power Consumption (Note 3)
Power Supply Rejection Ratio (50, 60 Hz) (Note 4) Voltage Channel (Gain = 10) Current Channel (All Gains) Notes: 3. All outputs unloaded. All inputs CMOS level.
4.
Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV zero-to-peak sine wave (frequency = 60 Hz) is imposed onto the +5 V supply voltage at VA+ and VD+ pins. The "+" and "-" input pins of both input channels are shorted to VA-. Then the CS5466 is put into an internal test mode and digital output data is collected for the channel under test. The zero-peak value of the digital sinusoidal output signal is determined, and this value is converted into the zero-peak value of the sinusoidal voltage that would need to be applied at the channel's inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB): 0.150V PSRR = 20 log ----------------- V eq
VOLTAGE REFERENCE
Parameter Reference Output Output Voltage VREFOUT Temperature Coefficient Load Regulation Reference Input Input Voltage Range Input Capacitance Input CVF Current VREFIN +2.5 4 70 V pF nA (Note 5) (Note 6) REFOUT TCVREF VR +2.4 +2.5 25 6 +2.6 60 10 V ppm/C mV Symbol Min Typ Max Unit
Notes: 5. The voltage at VREFOUT is measured across the temperature range. From these measurements the following
formula is used to calculate the VREFOUT Temperature Coefficient:.
TCVREF =
6.
AMAX
1 - TAMIN
6
Specified at maximum recommended output current of 1 A, source or sink.
6
(
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( (VREFOUTMAX - VREFOUTMIN) ( T VREFOUTAVG (
( 1.0 x 10
CS5466
DIGITAL CHARACTERISTICS
* * * *
(Note 7)
Min / Max characteristics and specifications are guaranteed over all operating conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = 5 V 5% VD+ = 3.3 V 5% or 5 V 5%; AGND = DGND = 0 V. All voltages with respect to 0 V. MCLK = 4.096 MHz
Parameter Master Clock Characteristics Master Clock Frequency Master Clock Duty Cycle CPUCLK Duty Cycle Filter Characteristics High-pass Filter Corner Frequency Input/Output Characteristics High-level Input Voltage XIN RESET Low-level Input Voltage (VD = 5 V) XIN RESET Low-level Input Voltage (VD = 3.3 V) XIN RESET High-level Output Voltage (except XOUT) Low-level Output Voltage (except XOUT) Input Leakage Current Digital Output Pin Capacitance Drive Current FOUT, E1, E2, NEG (Note 10) Iout = +5 mA Iout = -5 mA -3 dB (Note 8 and 9) Internal Gate Oscillator
Symbol MCLK VIH
Min 3 40 40 -
Typ 4.096 0.125
Max 5 60 60 -
Unit MHz % % Hz
(VD+) - 0.5 0.8 VD+ (VD+) - 1.0 -
1 5 50
1.5 0.2 VD+ 0.3 0.2 VD+ 0.4 10 -
V V V V V V V V A pF mA
VIL
VIL
VOH VOL Iin Cout IDR
Notes: 7. All measurements performed under static conditions.
8. 9. 10. If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification. The frequency of CPUCLK is equal to MCLK. VOL and VOH are not specified under this condition.
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SWITCHING CHARACTERISTICS
* * * * Min / Max characteristics and specifications are guaranteed over all operating conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = 5 V 5% VD+ = 3.3 V 5% or 5 V 5%; AGND = DGND = 0 V. All voltages with respect to 0 V. Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.
Parameter Rise Times Fall Times Start-up Oscillator Start-up Time Period Pulse Width Rising Edge to Falling Edge E1 Falling Edge to E2 Falling Edge FOUT Timing (Note 13 and 14) Period Pulse Width FOUT Low
12.
Symbol Digital Output (Note 11) Digital Output (Note 11) trise tfall tost t1 t2 t3 t4 t5 (Note 15) t6 t7
Min 500 250 250 250 0.10 -
Typ 50 50 60 1 / fFOUT 0.5*t5 0.5*t5
Max -
Unit ns ns ms ms ms ms ms ms
XTAL = 4.096 MHz (Note 12)
E1 and E2 Timing (Note 13 and 14)
90 -
ms ms
Notes: 11. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. 13. Pulse output timing is specified at MCLK = 4.096 MHz. Current and voltage signals are at unity power factor. See "Energy Pulse Outputs" on page 11. for more information on pulse output pins. 14. Timing is proportional to the frequency of MCLK. 15. When FREQ2 = 0, FREQ1=1 and FREQ0=1, FOUT will have a typical pulse width of 20 s at MCLK = 4.096 MHz.
t1
E1
t2
t4
t3
t1
t2
E2
t3
t5
FOUT
t6
t7
Figure 1. Timing Diagram for E1, E2 and FOUT (Not to Scale)
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ABSOLUTE MAXIMUM RATINGS
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter DC Power Supplies (Notes 16 and 17) Positive Digital Positive Analog (Notes 18, 19, 20) (Note 21) All Analog Pins All Digital Pins Symbol VD+ VA+ IIN IOUT PD VINA VIND TA Tstg Min -0.3 -0.3 - 0.3 -0.3 -40 -65 Typ Max +6.0 +6.0 10 100 500 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V mA mA mW V V C C
Input Current, Any Pin Except Supplies Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Output Current, Any Pin Except VREFOUT
Notes: 16. VA+ and AGND must satisfy {(VA+) - (AGND)} + 6.0 V.
17. VD+ and AGND must satisfy {(VD+) - (AGND)} + 6.0 V. 18. Applies to all pins including continuous over-voltage conditions at the analog input pins. 19. Transient current of up to 100 mA will not cause SCR latch-up. 20. Maximum DC input current for a power supply pin is 50 mA. 21. Total power dissipation, including all input currents and output currents.
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IIN PGA
4th Order Modulator
Sinc3
IIR
HPF
FREQ[2:0] IGAIN[1:0] HPF
Config
Digital Filter
Current Channel
N=400
E1
x
Sinc3
VIN
10x
2nd Order Modulator
N
IIR
HPF
Energy-toPulse Rate Converter
E2
FOUT
NEG
Digital Filter
Voltage Channel
Figure 2. Data Flow
4.
THEORY OF OPERATION
the IIR filter to compensate for the magnitude roll-off of the low-pass filtering operation. An optional digital high-pass filter (HPF in Figure 2) removes any DC component from the selected signal path. By removing the DC component from the voltage or current channel, any DC content will also be removed from the calculated average active (real) power as well.
The CS5466 is a dual-channel analog-to-digital converter (ADC) followed by a computation engine that performs an energy-to-pulse conversion. The flow diagram for the two data paths is depicted in Figure 2. The analog inputs are structured with two dedicated channels, voltage and current, then optimized to simplify interfacing to sensing elements. The voltage-sensing element introduces a voltage waveform on the voltage channel input VIN and is subject to a fixed 10x gain amplifier. A second-order deltasigma modulator samples the amplified signal for digitization. Simultaneously, the current sensing element introduces a voltage waveform on the current channel input IIN and is subject to four programmable gains. The amplified signal is sampled by a fourth-order delta-sigma modulator for digitization. Both converters sample at a rate of MCLK / 8. The over-sampling provides a wide dynamic range and simplified anti-alias filter design.
4.2
Active Power Computation
The instantaneous voltage and current data samples are multiplied to obtain the instantaneous power. The product is then averaged over 400 conversions to compute the active power value used to drive pulse outputs E1, E2, and FOUT. Output pulse rate of E1 and E2 can be set to one of four frequencies to directly drive a stepper motor or a electromechanical counter or interface to a microcontroller or infrared LED. The alternating output pulses of E1 and E2 allows for use with low-cost electromechanical counters. Output FOUT provides a uniform pulse stream that is proportional to the active power and is designed for system calibration. The FREQ[2:0] inputs set the output pulse rate of E1, E2, and FOUT. See "Energy Pulse Outputs" on page 11. for more details.
4.1
Digital Filters
The decimating digital filters on both channels are Sinc3 filters followed by fourth-order IIR filters. The single-bit data is passed to the low-pass decimation filter and output at a fixed word rate. The output word is passed to
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5.
5.1
FUNCTIONAL DESCRIPTION
Analog Inputs
5.2
High-pass Filter
The CS5466 is equipped with two fully differential input channels. The inputs VIN and IIN are designated as the voltage and current channel inputs, respectively. The full-scale differential input voltage for the current and voltage channel is 250 mVP.
By removing the offset from either channel, no error component will be generated at DC when computing the active power. Input pin HPF defines the three options:
- High-pass Filter (HPF) is disabled when pin HPF is connected high. - HPF is enabled in the voltage channel when pin HPF is connected low. - HPF is enabled in the current channel when pin HPF is connected to pin FOUT.
5.1.1
Voltage Channel
The output of the line-voltage resistive divider or transformer is connected to the VIN+ and VIN- input pins of the CS5466. The voltage channel is equipped with a 10x, fixed-gain amplifier. The full-scale signal level that can be applied to the voltage channel is 250 mV. If the input signal is a sine wave, the maximum RMS voltage is:
250mV P 2
5.3
Energy Pulse Outputs
----------------- 176.78mV RMS
which is approximately 70.7% of maximum peak voltage.
The CS5466 provides three output pins for energy registration. The E1 and E2 pins provide a simple interface from which energy can be registered. These pins are designed to directly connect to a stepper motor or electromechanical counter. The pulse rate on the E1 and E2 pins are in the range of 0 to 4 Hz and all frequency settings are optimized to be used with standard meter constants. The FOUT pin is designated for system calibration and the pulse rate can be selected to reach a frequency of 8000 Hz.
5.3.1
Pulse Output Format.
5.1.2
Current Channel
The output of the current-sense resistor or transformer is connected to the IIN+ and IIN- input pins of the CS5466. To accommodate different current-sensing devices, the current channel incorporates programmable gains which can be set to one of four input ranges. Input pins IGAIN1 and IGAIN0 (See Table 1) define the four gain selections and corresponding maximum input signal level. IGAIN1 IGAIN0 0 0 1 1 0 1 0 1 Maximum Input Range 250mV 50mV 25mV 16.67mV 10x 50x 100x 150x
The CS5466 produces alternating pulses on E1 and E2. This pulse format is designed to drive a stepper motor. Each pin produces active-low pulses with a minimum pulse width of 250 ms when MCLK = 4.096 MHz. Refer to "Switching Characteristics" on page 8 for timing parameters. The FOUT pin issues active-high pulses. The pulse width is equal to 90 ms (typical), unless the period falls below 180 ms. At this time the pulses will be equal to half the period. In mode 3 (FREQ[2:0] = 3), the pulse width of all FOUT pulses is typically 20 s regardless of the pulse rate (MCLK = 4.096 MHz).
5.3.2
Selecting Frequency of E1 and E2
Table 1. Current Channel PGA Setting For example, if IGAIN1=IGAIN0=0, the current channel's gain is set to 10x. If the input signals are pure sinusoids with zero phase shift, the maximum peak differential signal on the current or voltage channel is 250 mVP. The input signal levels are approximately 70.7% of maximum peak voltage producing a full-scale energy pulse registration equal to 50% of absolute maximum energy pulse registration. This will be discussed further in Section 5.3 Energy Pulse Outputs on page 11.
The pulse rate on E1 and E2 can be set to one of four frequency ranges. Input pins FREQ1 and FREQ0 (See Table 2) determine the maximum frequency on E1 and E2 for pure sinusoidal inputs with zero phase shift. As shown in Figure 1 on page 8, the frequency of E2 is equal to the frequency of E1 with active-low alternating pulses. As discussed in Section 5.1.2 Current Channel on page 11, the maximum frequency on the E1 and E2 output pins is equal to the selected frequency in Table 2 if the maximum peak differential signal applied to both channels is a sine wave with zero phase shift.
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Frequency Select FREQ2 0 0 0 0 1 1 1 1
Notes: 1 2 3
Maximum Frequency for a Sine Wave (Notes 1, 2 and 3) E1 or E2 0.125 Hz 0.25 Hz 0.5Hz 1.0 Hz 0.125 Hz 0.25 Hz 0.5 Hz 1.0 Hz E1+E2 0.25 Hz 0.5 Hz 1.0 Hz 2.0 Hz 0.25 Hz 0.5 Hz 1.0 Hz 2.0 Hz FOUT 64x(E1+E2) 32x(E1+E2) 16x(E1+E2) 2048x(E1+E2) 128x(E1+E2) 64x(E1+E2) 32x(E1+E2) 16x(E1+E2) 16 Hz 16 Hz 16 Hz 4,096 Hz 32 Hz 32 Hz 32 Hz 32 Hz
FREQ1 0 0 1 1 0 0 1 1
FREQ0 0 1 0 1 0 1 0 1
A pure sinusoidal input with zero phase shift is applied to the voltage and current channel. MCLK = 4.096 MHz See Figure 1 on page 8 for E1 and E2 timing diagram.
Table 2. Maximum Frequency for E1, E2, and FOUT
5.3.3
Selecting Frequency of FOUT
The pulse output FOUT is designed to assist with meter calibration. Using the FREQ[2:0] pins, FOUT can be set to frequencies higher than that of E1 and E2. The FOUT frequency is directly proportional to the E1 and E2 frequencies. Table 2 defines the maximum frequencies for FOUT and the dependency of FOUT on E1 and E2.
The absolute maximum pulse rate observed on E1 and E2, determined by the FREQ[2:0] selection is defined below in Table 3.
Frequency Select FREQ2 FREQ1 FREQ0 x x x x 0 0 1 1 0 1 0 1
Absolute Max Frequency E1 or E2 0.25 Hz 0.5 Hz 1.0 Hz 2.0 Hz E1+E2 0.5 Hz 1.0 Hz 2.0 Hz 4.0 Hz
5.3.4
Absolute Max Frequency on E1 and E2
The CS5466 supports input signals on the voltage and current channels that may not be a sine wave. A typical situation of achieving the absolute maximum frequency on E1 and E2 would be if a 250 mV dc signal is applied to the VIN and IIN input pins. The digital high-pass filter should be disengaged by selecting HPF = 1.
Table 3. Absolute Max Frequency on E1 and E2
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5.3.5 E1 and E2 Frequency Calculation
output pin will become active-high and will remain active-high until positive active power is detected. The NEG pin is valid at least 250ns prior to any assertion of E1 or E2, and FOUT, to indicate the sign of a given energy output. The NEG pin is updated at a rate of 10 Hz at MCLK = 4.096 MHz.
The pulse output frequency of E1 and E2 is directly proportional to the active power calculated from the input signals. To calculate the output frequency on E1 and E2, use the following transfer function:
5.5
FREQ E1,E2
Power-on Reset
=
VIN x 10 x IIN x IGAIN x PF x FREQ max ----------------------------------------------------------------------------------------------------------------2 VREFIN
FREQE1,E2 = Actual frequency of E1 and E2 pulses [Hz] VIN = rms voltage across VIN+ and VIN- [V] IIN = rms voltage across IIN+ and IIN- [V] IGAIN = Current channel gain selection (10, 50, 100, 150) PF = Power Factor FREQmax = Absolute Max Frequency for E1 and E2 [Hz] VREFIN = Voltage at VREFIN pin [V]
Upon powering up, the digital circuitry is held in reset until the analog voltage reaches 4.0 V. At that time, an eight-XIN-clock-period delay is enabled to allow the oscillator to stabilize. The CS5466 will then initialize. The device reads the control pins IGAIN[1:0], FREQ[2:0] and HPF, and begins performing energy measurements.
5.6
Oscillator Characteristics
XIN and XOUT are the input and output of an inverting amplifier which can be configured as an on-chip oscillator, as shown in Figure 3. The oscillator circuit is designed to work with a quartz crystal. To reduce circuit
Example: For a given application, assume a 50 Hz line frequency and a purely resistive load (unity power factor), the following configuration is used: - FREQ[2:0] = 3 FREQmax = 2 Hz - IGAIN[1:0] = 2 IGAIN = 100 - VREFIN = VREFOUT = 2.5 V In this configuration, the maximum sine wave that can be applied is 250 mVp on the voltage channel and 25 mVp on the current channel. Using the above equation, the output frequency of energy pulse E1 or E2 is calculated:
0.25V p x 10 x 0.025V p x 100 x 1 x 2Hz -------------------------------------------------------------------------------------------------------- = 1Hz 2 2 x 2 x 2.5V
XOUT C1
Oscillator Circuit
XIN C2
DGND
C1 = C2 = 22 pF
Figure 3. Oscillator Connection cost, two load capacitors C1 and C2 are integrated in the device, one between XIN and DGND and the other between XOUT and DGND. Lead lengths to/from the crystal should be minimized to reduce stray capacitance. To drive the device from an external clock source, XOUT should be left unconnected while XIN is driven by the external circuitry. There is an amplifier between XIN and the digital section which provides CMOS-level signals. This amplifier works with sinusoidal inputs so there are no problems with slow edge times.
With maximum pure sinusoidal input signals, the frequency of E1 or E2 is half the absolute maximum frequency set with FREQ[2:0]. To calculate the frequency of FOUT for the example above, assume FREQ2 = 0.
FOUT = 2048 x ( E1 + E2 ) = 2048 x 2Hz = 4096Hz
5.4
Energy Direction Indicator
The NEG pin indicates the sign of the calculated active power. If negative active power is detected, the NEG
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5.7 Basic Application Circuit
shunt resistor configuration, the common-mode level of the CS5466 must be referenced to the line side of the power line. This means that the common-mode potential of the CS5466 will track the high voltage levels, as well as low voltage levels, with respect to earth ground potential.
Figure 4 shows the CS5466 configured to measure power in a single-phase, 2-wire system while operating in a single-supply configuration. In this diagram, a shunt resistor is used to sense the line current and a voltage divider is used to sense the line voltage. In this type of
N
120 VAC
L 500 470 nF 500 + 470 F 0.1 F
14 3
10
10 k
1 F
0.1F
+
AGND VA+
9
VD+
VIN+
C V+
R2
R1
RV-
C V-
CVdiff
10
RESET EDIR / P4 E2 E1
FOUT NEG
19
21 22 18
Stepper Motor
VIN-
6 17 20 23 7 5
Calibratio n Resistor
15
IIN-
RIRSHUNT RI+
C IC I+
CIdiff
16
FREQ2 FREQ1 FREQ0 IGAIN1 IGAIN0
IIN+
5466 Config. Settings
IHPF
XOUT
12
8
1
VREFIN XIN VREFOUT CPUCLK DGND
4
4.096 MHz
24 2
11
0.1 F
AGND VA13
Note: Indicates common (floating) return.
Figure 4. Typical Connection Diagram
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6. PACKAGE DIMENSIONS
24L SSOP PACKAGE DRAWING
N
D
E11 A2 A1 A
E
2
L
e
b
END VIEW
SIDE VIEW
123
SEATING PLANE
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025 0
INCHES NOM -0.006 0.068 -0.323 0.307 0.209 0.026 0.03 4
MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041 8
MIN -0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63 0
MILLIMETERS NOM -0.13 1.73 -8.20 7.80 5.30 0.65 0.75 4
NOTE MAX 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.75 1.03 8
2,3 1 1
JEDEC #: MO-150 Controlling Dimension is Millimeters. Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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CS5466
7. ORDERING INFORMATION
Model Temperature Package
CS5466-IS CS5466-ISZ (lead free)
-40 to +85 C
24-pin SSOP
8.
ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number Peak Reflow Temp 240 C 260 C MSL Rating* 2 3 Max Floor Life 365 Days 7 Days
CS5466-IS CS5466-ISZ (lead free)
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
9.
REVISION HISTORY
Date SEP 2004 OCT 2004 JUN 2005 AUG Initial Release Corrected table heading on Page 6. Minor edits Updated with most-current characterization data. corrected energy pulse output rate equation on p13. Added MSL data. Changes PP1 PP2 PP3 F1
Revision
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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DS659F1

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